Coupling device using buried capacitors in multilayered substrate

ABSTRACT

The present invention proposes a coupling device, comprising a substrate ( 1 ), a conductive layer ( 2 ) covering a first surface of said substrate ( 1 ), at least two electromagnetically coupled lines ( 3   a,    3   b ) being provided opposite to said first surface and at least one thereof being covered by at least one cover layer ( 4, 5 ) wherein at least one capacitor (C 1,  C 2,  C 3,  C 4 ) is connected between a first end of at least one of said at least two lines ( 3   a,    3   b ) and said conductive layer ( 2 ). The at least one capacitor is a buried capacitor grounded in order to equalize unequal phase velocities otherwise degrading the performance of e.g. broadside coupled structures in an inhomogeneous substrate structure such as for example microstrips in a multilayer LTCC. Therefore the present invention enables coupling devices having a high performance and offering in that way the best of all possible design scenarios in terms of wideband performance, size and cost.

FIELD OF THE INVENTION

The present invention relates to a coupling device. More particularly,the present invention relates to a coupling device obtainable from amultilayer integrated circuit technology fabrication process.

BACKGROUND OF THE INVENTION

Coupling devices (referred to as couplers) in general, such as forexample Hybrid 3 dB couplers, are essential circuit components which areincreasingly being used for high performance applications in suchdiverse circuits as RF mixers, amplifiers and modulators. In additionthey can be used in a variety of other support functions such as theones encountered in general RF signal and amplitude conditioning anderror signal retrieval systems.

The expression “hybrid” in connection with couplers means an equal splitof power between two (output) ports of the coupler with respect to aninput port. Hence a 3 dB coupler is a “hybrid” since:10 log(Power_(out)/Power_(in))=−3 dBPower_(out)/Power_(in)=10^((−3/10))=0.5So the output power Powerout of one of the output ports is half (−3 dB)of the input power Power_(in), the other half emerges from the otheroutput port. If we consider FIG. 1 (to be explained in greater detaillater on) and say that port P1 is the input port, then port P4 is saidto be the coupled port and port P2 is said to be the direct port withhalf the input power being output from each of the output ports. Port P3is said to be isolated from port P1. Note that the output at the coupledport will experience a phase shift dependent on the coupling length,while the output at the direct port will not experience a phase shift(with reference to the input supplied at the input port).

The use of couplers in the 1–5 GHz range though has been at the expenseof large area of occupation required for such couplers and fabricationtolerance problems resulting from tight gap dimensioning for 3 dBcoupling operation when implemented in PCB technology (PCB=PrintedCircuit Board). More precisely, when implementing a coupler in PCBtechnology, it is necessary to accurately provide a gap between couplinglines of a coupler with the designed dimensions, since otherwise thecoupler will not perform properly.

To address fabrication issues, narrow-band equivalents that compromiseeven more the size of the circuit such as branch line couplers have beenutilized. Other alternatives such as SMD type (SMD=Surface MountedDevice) hybrid couplers have been used that offer better size ratios butare still quite large for future systems of small size with increasedfunctionality. Often SMD component type couplers require additionalexternal matching components to optimize their performance in terms ofisolation and matching as well as amplitude and phase balance andtherefore even further compromise the circuit area. Stated in otherwords, the provision of externally provided SMD components for matchingpurposes further increases the entire size of the coupler and requiresadditional soldering processes for soldering the externally provided SMDcomponents. The increased use of SMD components increases costs and theuse of soldering connections compromises the environmental friendlinessand reduces the reliability of a manufactured subsystem module, sinceeach solder connection represents a potentially source of errors.

Stripline technology has also been utilized for the design of highperformance couplers but it suffers from the need to accommodate forlarger volume/size for a given component inflicting additionally morematerials costs.

Low loss performance can also be an issue especially in LNA designs(LNA=Low Noise Amplifier) as well as in high efficiency poweramplification and linearisation applications. For such applications thedB on loss performance is a critical issue. Current designs offertypically 0.3 dB loss performance per coupler.

To rectify the above problems and address the performance requirementsof future miniaturized circuit subsystems, wideband couplers in terms ofisolation, matching and amplitude and phase balance are required thatare additionally fabrication tolerance resistant and of much smallersize than its predecessors.

Size can be decreased by using an appropriate integration technology aswell as a miniaturization circuit technique. Multilayer integratedcircuits such as multilayer ceramic LTCC/HTCC (LTCC=Low TemperatureCofired Ceramics, HTCC=High Temperature Cofired Ceramics) technologieshave been identified as a technology of great miniaturization potentialsince three dimensional design flexibility is combined with ceramicmaterials of high dielectric constant (∈). Loss performance is enabledby the careful choice of materials and circuit geometry as well astopology.

Isolation/matching and amplitude and phase balance performance can beoptimized by using a suitable circuit technique or geometry.

FIG. 1 shows an equivalent circuit diagram of a conventionally knowncoupler. Basically, a coupling device consists of a pair of coupledlines 3 a, 3 b. Each line has two ports for inputting/outputtingelectrical and/or electromagnetic signals to be coupled. Thus, as shownin FIG. 1, the line 3 a has ports P1, P2, while the line 3 b has portsP3, P4. Each port P1 through P4 is terminated with a terminationimpedance Z₀. In a 50 Ohms system, the value of Z₀ is set to 50 Ohms.The lines 3 a, 3 b have equal length which is expressed in terms of thewavelength for which the coupler is designed. The parameter le° denotesthe electric length of the coupler which is measured in degrees (°). Forexample, for the coupler shown in FIG. 1, the length is assumed to beλ/4, with λ being the center frequency of operation for which thecoupler is designed. Thus, in such a case, a signal fed to the couplerat port P1 and used as a reference is coupled to the port P4 (coupledport) with its phase shifted (indicated by “−90°”). Port P3 is isolatedfrom port 1, which means that no power reaches port P3 from port P1. Thesignal at port P2 (the direct port) is not shifted with reference to thesignal input at port P1 as indicated by 0°. Note that in case of a 3 dBcoupler as an example, the power input at port P1 is split between portsP2 (direct port) and P4 (coupled port) Nevertheless, other line lengthssuch as λ/2, or odd multiples of λ/4 such as 3λ/4 are possible. Also,the lines could have different lengths, while in such a case only thelength of the lines over which the lines are facing each otherrepresents an effective coupling length (electric length le in [°]). Thecoupler, i.e. the coupling lines, may be described in terms of the evenand odd propagation modes of electromagnetic waves travelling therethrough and their respective characteristic impedances Z_(oo), Z_(oe)and phase velocities υ_(oe) and υ_(oo) and the electric length le of thecoupling lines.

In 3 dB coupling in a 50 Ohms system, one needs to design the lines tohave impedance values Z_(oo) and Z_(oe) of 20.7 and 120.7 Ohmsrespectively. The above arrangement though assumes equal phasevelocities for the even and the odd modes i.e. υ_(oe)=υ_(oo).

If the phase velocities of the two modes (even and odd mode) areunequal, then isolation and matching at the centre frequency ofoperation suffers. More precisely, the undesired unequal phasevelocities are typical for all transmission lines that are not strictlyTEM (Transverse-Electro-Magnetic), often referred to as Quasi-TEMtransmission lines such as for example a microstrip line. This isinvariably the case with most couplers that use a pair of microstriplines.

The problem of unequal phase velocities could be prevented by the use oftrue TEM transmission lines such as coupled striplines. However, in sucha case at least one extra metallization layer is required which is notdesired in terms of costs, involved.

FIG. 7 shows in a rough outline the difference between a stripline andmicrostrip arrangement, respectively. The left hand portion of FIG. 7shows a stripline arrangement, while the right hand portion shows amicrostrip arrangement. It is an important property of any two-conductorlossless transmission lines (coupling lines) placed in a uniformdielectric substrate (homogeneous and/or symmetrical substrate) that itsupports a pure TEM mode of propagation. A common example of these typesof lines is STRIPLINE, as shown in FIG. 7, left portion. However if atransmission line is placed in an inhomogenous (and/or non-symmetric)dielectric substrate it can no longer support fully-TEM propagationbecause the electromagnetic wave now propagates mostly within thesubstrate, but some of the wave is now able to propagate in air also.The most common example of this is MICROSTRIP also shown in FIG. 7,right portion. Stripline couplers are encased in a homogenous substratewhere the electromagnetic fields of the coupler are confined within thesubstrate by the two ground planes (conductive layers) While for amicrostrip line its electromagnetic propagation takes place mainlywithin the substrate (in fact most of the power propagates within thesubstrate), but some of the power propagates outside the substrate whichis usually air.

FIG. 2 shows a cross section of a coupler (in microstrip arrangement) asrepresented in FIG. 1, while FIG. 2 shows coupled lines on the surface(FIG. 2 a) or embedded (FIG. 2 b) within a substrate as alternativemicrostrip arrangement implementations.

As shown in FIG. 2( a), the coupling device comprises a substrate 1 madeof a dielectric material of a dielectric constant ε_(r), a conductivelayer 2 covering a first surface of said substrate 1 (the “bottom”side), and (at least) two lines 3 a, 3 b being provided electricallyseparated from each other at a second surface of said substrate 1opposite to said first surface (the “top” side). Note that the samereference numerals as those used in FIG. 1 denote the like componentssuch that a repeated explanation thereof is omitted. Said two lines 3 a,3 b are laterally spaced apart from each other, with the amount ofspacing (i.e. the width of a gap there between) adjusts the degree ofelectromagnetic coupling between said two lines. Although only two linesare shown, more than two lines may be used for coupling purposesdependent on the specific purpose for which the coupler is designed.Moreover, said conductive layer 2, in operation of the device, isconnected to ground potential.

The coupler shown in FIG. 2( a) is generally known as an edge coupledcoupling device, since coupling occurs between the elongated sides/edgesin lengthwise direction of the lines facing each other (in a directionvertical to the drawing plane in FIG. 2( a)).

It is typical in such edge coupled microstrip line couplers that the oddmode velocity is higher than the even mode velocity i.e. υ_(oo)>υ_(oe).Compensation techniques that improve isolation and matching and retainthe amplitude and phase balance to good bandwidths have been dealt withpreviously. The main issue with these techniques is that such edgecoupled couplers suffer from fabrication tolerances (gap dimensionrequirement such as small gap, constant over the entire length of thestriplines), and therefore their use is not generally suggested.

The case when the even mode velocity is higher than the odd modevelocity (i.e. υ_(oe)>υ_(oo)) is a case that is encountered in the caseof partially embedded broadside coupled microstrips (i.e. at least onecoupling line being embedded).

Such a broadside coupled coupling device is illustrated in FIG. 2( b).Note that the same reference numerals as those used in FIG. 1 denote thelike components such that a repeated explanation thereof is omitted. Asshown, a broadside coupled coupling device comprises a substrate 1 madeof a dielectric material of a dielectric constant ∈_(r), a conductivelayer 2 covering a first surface of said substrate 1 (the “bottom”side), (at least) two electromagnetically coupled lines 3 a, 3 b beingprovided opposite to said first surface and being covered by at leastone cover layer 4, 5.

The (at least) two lines 3 a, 3 b are arranged at different distancesfrom said first surface of said substrate 1, with a difference betweenthe distances in which said two lines 3 a, 3 b are arranged from saidfirst surface of said substrate 1 is determined by a thickness of afirst cover layer 4 covering a first line 3 b of said at least twolines. As shown in FIG. 2( b), the first line 3 b and second line 3 a ofsaid two lines are arranged such that they fully overlap each other inthe cross-sectional representation. Nevertheless, this is not absolutelyrequired and it is sufficient that they at least partly overlap eachother. The amount of overlap (and of course the distance between thelines in “vertical” direction within the substrate) adjusts the degreeof electromagnetic coupling between said at least two lines. Such anoverlap is illustrated in FIG. 3B.

A second cover layer 5 is arranged to cover at least the second line 3 aof said two lines. This means that as shown, the second cover layer 5also covers the first cover layer. However, this is not absolutelyrequired, while from a viewpoint of simplified production neverthelessdesirable. The at least one cover layer 4, 5 is for example of the samematerial as said substrate 1. Moreover, said conductive layer 2, inoperation of the device, is connected to ground potential.

Note that the arrangement shown in FIG. 2( a) may additionally becovered with a cover layer (not shown) so that either an edge coupledburied coupling device is obtained in case the cover layer is adielectric material (e.g. the same as the substrate material), or anedge coupled coated coupling device is obtained in case the cover layeris e.g. a resist pattern.

FIG. 3 shows a further arrangement of a coupling device. FIG. 3B shows acoupling device in cross section with at least partly overlappingcoupling lines as mentioned herein above. FIG. 3A shows a top viewand/or layout view of the coupling device shown in FIG. 3B. Ports P1 andP2 are interconnected by the coupling line 3 a which is arranged abovethe coupling line 3 b interconnecting ports P4 and P3. Coupling line 3 aand ports P1, P2 are illustrated in a differently hatched illustrationas compared to coupling line 3 b and ports P4 and P3.

Still further, the arrangements of FIGS. 2( a) and 2(b) and or FIG. 3may be combined if e.g. more than two coupled lines are present in thecoupling device. This means that for example edge coupled coupling linesmay in turn be broadside coupled to one or more other coupling linesprovided for in the arrangement.

Note also, that as the production technology for such devices, themultilayer integrated circuit technology which is assumed to be wellknown to those skilled in the art may be used so that a detaileddescription of the method for production of such devices is consideredto be dispensable.

To the best of our knowledge there have not been suggested anytechniques that compensates the velocity of the even and odd modes whenthe situation is encountered that the even mode velocity is higher thanthe odd mode velocity. Thus, in such a case, the above discussedproblems inherent to coupling devices in connection with unequal phasevelocities still remain.

SUMMARY OF THE INVENTION

Consequently, it is an object of the present invention to provide acoupling device which is free from such drawbacks inherent to couplingdevices in connection with unequal phase velocities.

According to the present invention, this object is for example achievedby a coupling device, comprising a substrate, a conductive layercovering a first surface of said substrate, at least twoelectromagnetically coupled lines being provided opposite to said firstsurface and at least one of which lines being covered by at least onecover layer, wherein at least one capacitor is connected between a firstend of at least one of said at least two lines and said conductivelayer.

Advantageous further developments are as defined in the respectivedependent claims.

Accordingly, a coupling device according to the present invention isproposed as a circuit technique that optimizes the coupler performancein terms of isolation and matching. This technique is particularlysuited to a practical circuit topology that can be implemented inLTCC/HTCC technology while this topology is also suited for low lossperformance and has increased miniaturization potential. As such both,i.e. size and performance can be optimized while the added performancecan be used to trade off with any fabrication tolerances incurred duringfabrication.

In addition, using the proposed technique all the performance propertiescan be retained over a wide bandwidth. The technique is also suited tomultilayer IC (IC=Integrated Circuit) technologies such as the onesencountered for example in multilevel metal SiGe (Silicon-Germanium) andmultilayer thin film processes. It should be noted though that the costof implementing couplers in the 1–6 GHz region well justifies the use ofmultilayer ceramic integrated circuit technology (e.g. LTCC) as opposedto the significantly more expensive Si/GaAs (silicon/gallium arsenide)IC and thin film approaches.

The invention presents a signal coupling structure with a new (unequalphase velocity) compensation method applied in a multilayer structure.The unequal phase velocities of two coupled microstrip lines arecompensated by using buried capacitors in the multilayer structure. Inparticular, the present invention is applicable to broadside coupledmicrostrips arrangements. Buried capacitors are added in order tocompensate the unequal phase velocities related to two broadside coupledmicrostrip lines. After the phase velocities are compensated (i.e. theat least one capacitor is added), the phase velocities of the two modesare equal and therefore no forward coupling exists: Thus, the isolationis improved significantly.

As integrated in the multilayer ceramic substrate, this structure savescost and size. Also, it increases the reliability, since no SMDcomponents are required. Electrical performance, especially isolation,is enhanced by the use of the capacitors.

According to the present invention, a novel compensation technique hasbeen suggested that among others enables the use of broadside coupledmicrostrip line components embedded in multilayer structures.

The technique effectively enables a design topology that though itoffers structural convenience, miniature size and low loss performance,would otherwise suffer from low isolation and matching performance.

Therefore the present invention enables coupling devices having a highperformance combined with the above advantages, offering in that way thebest of all possible design scenarios in terms of wideband performance,size and cost.

The coupling device according to the present invention is particularlysuitable for being used for high performance applications in suchdiverse circuits as RF mixers, amplifiers (e.g. low noise amplifiersLNA) and modulators. In addition it can be used in a variety of othersupport functions such as the ones encountered in general RF signal andamplitude conditioning and error signal retrieval systems.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more readily understood upon referring to theaccompanying drawings, in which:

FIG. 1 shows an equivalent circuit diagram of a conventionally knowncoupler;

FIG. 2 shows a cross section of a coupler as represented in FIG. 1, withFIG. 2 showing coupled lines on the surface of (FIG. 2) or embedded(FIG. 2 b) within a substrate;

FIG. 3A shows a layout (top view) of a coupling device according to amodification of the coupler shown in FIG. 2( b),

FIG. 3B shows a cross section of a coupler as represented in its layoutin FIG. 3A;

FIG. 4 shows an equivalent circuit diagram of a coupling deviceaccording to the present invention;

FIG. 5A shows a layout (top view) of a coupling device according to thepresent invention as shown in FIG. 4,

FIG. 5B shows a cross sectional view through the ports P1–P4 of thecoupling device shown in FIG. 5A;

FIG. 5C shows a top view on an alternative capacitor implemention;

FIG. 5D shows a cross sectional view of such an alternative capacitorimplementation being incorporated in the coupling device

FIG. 6A shows a plot of measurement results for a conventional coupler,while

FIG. 6B shows a plot of measurement results for a coupling deviceaccording to the present invention; and

FIG. 7 shows a structural comparison between basic stripline andmicrostrip coupler device arrangements.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Subsequently, the present invention will be described in detail withreference to the accompanying drawings.

FIG. 4 shows an equivalent circuit diagram of a coupling deviceaccording to the present invention. The arrangement is rather similar tothe circuit arrangement as explained as an example with reference toFIG. 1. Thus, the same reference signs denote similar and/or identicalcomponents and a repeated explanation thereof is dispensed with.

The difference between the equivalent circuits shown in FIG. 1 and FIG.4 resides in that in the circuit according to FIG. 4, groundedcapacitors C1 through C4 are connected at the output ports P1 to P4,respectively. With the values of capacitance of the capacitors C1 to C4being properly chosen, the phase velocity mismatch between odd and evenmodes can be compensated for, i.e. equalized. The proper values ofcapacitance of the capacitors C1 to C4 depend on the degree of velocitymismatch. These proper values are determined before manufacturing on thebasis of e.g. simulation results of the coupler based on the other knownparameters of the coupler device.

Note that although FIG. 4 shows four capacitors, according to thepresent invention it is not necessarily the case that four capacitorsare connected. Rather, at least one capacitor (C1, C2, C3, C4) isconnected to a first end (i.e. at one of ports P1, P2 or P3, P4) of atleast one of said at least two lines 3 a, 3 b, and grounded. It is alsoto be noted that the present invention is not limited to λ/4 linelengths but may be applicable to all conceivable coupling line lengthssuch as for example λ/2 or 3λ/4.

Note also that the capacitors, upon manufacturing the device, are onlyadapted to be grounded, i.e. connectable to ground, while the respectiveactual connection to ground is established only when operating thedevice.

As mentioned beforehand, FIG. 2 shows the typical structural cases inwhich unequal phase velocities (which have to be compensated) may occur.FIG. 2( b) is a specific case of the arrangement generally shown in FIG.3B. This will serve as an example to which the proposed novel techniqueaccording to the present invention will be applied. The presentinvention being for example applied to such a broadside coupledmicrostrip structure as shown in FIG. 3B, is shown in FIG. 5B.

FIG. 5B shows a cross sectional view through the ports P1–P4 of thecoupling device shown in FIG. 5A. FIG. 5A shows a layout (top view) of acoupling device according to the present invention as shown in FIG. 4.

Generally, the broadside coupled microstrip structure is a very usefuldesign structure that can adjust the amount of coupling by the amount ofoffset between the two microstrip lines. (For example, it may roughly besaid to be adjusted to its maximum coupling degree in case of no offset(see FIG. 2( b)) and be adjusted towards its minimum coupling degreewith increasing offset). Nevertheless, although as an example only thepresent invention is applied to a structure as shown in FIG. 3B,resulting in an arrangement shown in FIG. 5B, it is to be noted that thepresent invention may also be applied to structure as shown in FIG. 2(b), or a combination of the structures illustrated in FIGS. 2( b) and/or3B (the combined structure then having at least three coupling lines).

In FIG. 5B the same reference signs denote the same or like componentsas in the previous Figures. The difference between FIG. 5B and FIG. 3Bresides in the provision of buried capacitors C1, C4. More precisely, C1and C4, respectively, in FIG. 5B denote a conductive member embedded insaid substrate 1 and facing said conductive layer 2 covering said firstsurface of said substrate 1. The conductive member may be any suitableconductive member that may have been applied for example by suitablelithography techniques to the substrate 1 and was thereafter buried byadditionally applied substrate material. Note that the conductive membermay be provisioned by depositing conductive material in the desiredshape for the member using known deposition processes such as CVD(Chemical Vapor Deposition) or PVD (Physical Vapor Deposition)processes, or using known (thin or thick) film printing processesapplying e.g. a conductive paste, or by using selective etchingprocesses etching away excess parts of a conductive member, etc.Generally, it should be noted that the present invention is notrestricted to any particular multilayer process but that any suitablemultilayer process technology may be used.

Each of such members is connected by means of a respective electricalconnection W1, W4 from said first end (i.e. port P1, P4) of said atleast one of said (at least) two lines 3 a, 3 b to said conductivemember C1, C4. Such a connection may be established by providing a viahole connection.

Note that the capacitance of said capacitors (C1 to C4) is determined bythe area of said conductive member C1, C4, the distance between saidconductive member C1, C4 and said conductive layer 2 covering said firstsurface of said substrate 1, and the dielectric constant ∈_(r) of saidsubstrate 1 there between. It is to be noted that although the membersC1 and C4 in FIG. 5B are shown to be equally spaced apart from theconductive layer 2, it is also conceivable that according to therequired capacitance value required for a specific case, the members C1,C4 may be located at different distances from the conductive layer 2. Insuch a case, however, the production would require more productionsteps. (If e.g. all four conductive members involved in constituting thecapacitors in the chosen example are at the same distance from theconductive layer, one production sub-cycle for providing the members isneeded, while if all four conductive members involved in constitutingthe capacitors are at a different distance from the conductive layer,four such production sub-cycles for providing the members are needed.)

Note that the coupling line 3 a in FIG. 5B need not necessarily becovered by a cover layer 5, but that the cover layer 4 covering couplingline 3 b and separating the coupling lines 3 b, 3 a from each other invertical direction, could be sufficient. Further, cover layers 4 and/or5 may be of the same material as the substrate 1, but are not limited tosuch a material so that the multilayer arrangement may comprise layers(substrate/cover layer(s)) of different dielectric constants, ifappropriate. Even the cover layers 4 and 5 may be of differentmaterial's each of which differs from the substrate material.

FIG. 5C illustrates an alternative for implementing a capacitoraccording to the present invention. There are two common forms ofcapacitors that are practically used in real implementation of thecoupling device according to the present invention. One is referred toas a parallel plate capacitor as explained above in connection with FIG.5B, while the other is named an “interdigitated” capacitor (see FIG.5C). The interdigitated capacitor may particularly be used to achievesmall value capacitors. As shown in FIG. 5C, its capacitor value isprimarily defined by the number of fingers it has (N), the width of eachfinger (W), the separation between each finger (S), the length of eachfinger (L), and the dielectric constant (εr) of the substrate. One partof the conductive member constituting an interdigitated capacitor isconnected, e.g. by means of a via hole connection, to the conductivelayer 2 serving as a ground plane in operation of the coupling device.Note that the interdigitated capacitor, i.e. its two interdigitatedparts are located in one plane.

FIG. 5D shows a partly cross section through the interdigitatedcapacitor of FIG. 5C along the dashed line in FIG. 5C, when such acapacitor is connected to a coupling line in a substrate. Same referencenumerals denote the same or like components as in the previous Figures.FIG. 5D thus illustrates an example case in which capacitor C4 isrealized as an interdigitated structure, one part thereof beingconnected with via connection W4 to line 3 b while the other partthereof being connected by means of another connection W5 (via holeconnection) to the conductive layer 2. Note that one or more or even allcapacitors may be interdigitated capacitors and may also be used incombination with one (or more) parallel plate capacitor(s). Note thatFIG. 5D only shows a part of the entire coupling structure and forexample cover layer 5 and line 3 a are omitted from the representationin FIG. 5D. Also, the scale in FIG. 5D may deviate from a drawing scaleused in other figures. Additionally, the coupling device is not shown inits entire length but only its region at port P4 is shown.

Since the capacitors (conductive members) are below the structure of themicrostrip lines 3 a, 3 b, the area of the circuit is not increased. Thecapacitors are effectively being created monolithically within themultilayer structure and there is no need to use SMD capacitivecomponents that would adversely affect the performance. The circuit canbe designed as a whole, thus electromagnetically guarantying itsperformance.

5A shows a layout (top view) of a coupling device according to thepresent invention. FIG. 5A is substantially similar to FIG. 3A with theexception that the conductive members C1, C4 constituting the capacitorsC1, C4 (in FIG. 5B) and the conductive members C2, C3 are additionallyshown. Note that the coupling lines 3 a, 3 b are designed as a meandertype line in order to further decrease the required area for thecoupling device.

The present inventors have manufactured prototypes of embedded broadsidecoupled line 90° (λ/4) coupling devices and measured their performancein order to validate the proposed technique. One coupling device (seeFIGS. 3A, 3B) was fabricated without the present invention beingimplemented, while the other was fabricated with the present inventionbeing implemented (see FIGS. 5A, 5B)

In FIG. 6 the S-parameter responses S1, S22, S33, S44 (in dB) of theinput return loss at each of the four ports P1 to P4 are plotted versusfrequency (in GHz). This is shown in the respective upper plot of FIGS.6A and 6B. The input return loss is the ratio between the energyreturned at a port i and the energy input at said port i. (In the chosenexamples described herein, i ranges from i=1 to 4). Also, in therespective lower plots of FIGS. 6A and 6B, the S-parameter responses S31and S42 of the through parameters (in dB) are plotted versus frequency(in GHz). The through parameter S_(ki) is the ratio of the energy outputat a port k when input at a port i. (Note that port P3 is isolated fromport P1, while also port P4 is isolated from port P2) Both couplers weredesigned to operate in the 1750 MHz frequency range, and the results onisolation and matching for the two cases are presented in FIGS. 6A and6B, respectively. It may be seen from FIG. 6A that the uncompensatedcoupler offers low performance that would be not acceptable in practicalapplications while the compensated novel coupler (FIG. 6B) offerssuperior performance with better than −22 dB matching at all ports andbetter than −26 dB isolation.

Accordingly, as has been described herein above, the present inventionproposes a coupling device, comprising a substrate 1, a conductive layer2 covering a first surface of said substrate 1, at least twoelectromagnetically coupled lines 3 a, 3 b being provided opposite tosaid first surface and at least one thereof being covered by at leastone cover layer 4, 5, wherein at least one capacitor C1, C2, C3, C4 isconnected between a first end of at least one of said at least two lines3 a, 3 b and said conductive layer 2. The at least one capacitor is aburied capacitor grounded in order to equalize unequal phase velocitiesotherwise degrading the performance of e.g. broadside coupled structuresin an inhomogeneous substrate structure such as for example microstripsin a multilayer LTCC. Therefore the present invention enables couplingdevices having a high performance and offering in that way the best ofall possible design scenarios in terms of wideband performance, size andcost.

Although the present invention has been described herein above withreference to its preferred embodiments, it should be understood thatnumerous modifications may be made thereto without departing from thespirit and scope of the invention. It is intended that all suchmodifications fall within the scope of the appended claims.

1. A coupling device, comprising: a substrate, a conductive layercovering a first surface of said substrate, at least twoelectromagnetically coupled lines being provided opposite to said firstsurface and at least one thereof being covered by at least one coverlayer, characterized in that at least one capacitor is connected betweena first end of at least one of said at least two lines and saidconductive layer, wherein said capacitor is constituted by a conductivemember embedded in said substrate and facing said conductive layercovering said first surface of said substrate, and an electricalconnection from said first end of said at least one of said at least twolines to said conductive member.
 2. A coupling device according to claim1, wherein said at least two lines are arranged at different distancesfrom said first surface of said substrate.
 3. A coupling deviceaccording to claim 2, wherein a difference between the distances inwhich said at least two lines are arranged from said first surface ofsaid substrate is determined by a thickness of a first cover layercovering a first line of said at least two lines.
 4. A coupling deviceaccording to claim 2, wherein a first line and a second line of said atleast two lines are arranged such that they at least partly overlap eachother.
 5. A coupling device according to claim 3, further comprising: asecond cover layer arranged to cover at least a second line of said atleast two lines.
 6. A coupling device according to claim 4, wherein theamount of overlap adjusts the degree of electromagnetic coupling betweensaid at least two lines.
 7. A coupling device according to claim 1,wherein said connection is a via connection.
 8. A coupling deviceaccording to claim 1, wherein the capacitance of said capacitor isdetermined by the area of said conductive member, the distance betweensaid conductive member and said conductive layer covering said firstsurface of said substrate, and the dielectric constant of saidsubstrate.
 9. A coupling device according to claim 1, wherein said atleast one cover layer is of the same material as said substrate.
 10. Acoupling device according to claim 1, wherein said substrate is made ofa dielectric material.
 11. A coupling device according to claim 1,wherein said conductive layer is connectable to ground potential.